Intel 82540EP - Manual (Page 12)

82540EP — Networking Silicon
6 Datasheet
2.3 PHY Specific Features
2.4 Host Offloading Features
Features Benefits
Integrated PHY for 10/100/1000 Mbps full and half
duplex operation • Smaller footprint and lower power dissipation
compared to multi-chip MAC and PHY solutions
IEEE 802.3ab Auto-Negotiation support
• Automatic link configuration including speed,
duplex, and flow control
IEEE 802.3ab PHY compliance and compatibility
• Robust operation over the installed base of
Category-5 (CAT-5) twisted pair cabling
State-of-the-art DSP architecture implements digital
adaptive equalization, echo cancellation, and cross-
talk cancellation • Robust performance in noisy environments
• Tolerance of common electrical signal
impairments
PHY ability to automatically detect polarity and cable
lengths and MDI versus MDI-X cable at all speeds • Easier network installation and maintenance
• End-to-end wiring tolerance
Features Benefits
Transmit and receive IP, TCP and UDP checksum off-
loading capabilities
• Lower CPU utilization
Transmit TCP segmentation
• Increased throughput and lower CPU utilization
• Large send offload feature (in Microsoft*
Windows* XP) compatible
Advanced packet filtering
• 16 exact matched packets (unicast or multicast)
• 4096-bit hash filter for multicast frames
• Promiscuous (unicast and multicast) transfer
mode support
• Optical filtering of invalid frames
IEEE 802.1q VLAN support with VLAN tag insertion,
stripping and packet filtering for up to 4096 VLAN tags
• Ability to create multiple virtual LAN segments
Descriptor ring management hardware for transmit
and receive
• Optimized fetching and write-back mechanisms for
efficient system memory and PCI bandwidth
usage
16 KByte jumbo frame support
• High throughput for large data transfers on
networks supporting jumbo frames
Interrupt coalescing (multiple packets per interrupt)
• Increased throughput by reducing interrupts
generated by transmit and receive operations