Intel 82540EP - Manual (Page 29)

Networking Silicon — 82540EP
Datasheet 23
4.5.1.2 PCI Bus Interface Timing
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
Table 15. PCI Bus Interface Timing Parameters
Symbol Parameter
PCI 66MHz PCI 33 MHz
Units
Min Max Min Max
TVAL
CLK to signal valid delay: bussed
signals
2 6 2 11 ns
TVAL(ptp)
CLK to signal valid delay: point-
to-point signals
2 6 2 12 ns
TON Float to active delay 2 2 ns
TOFF Active to float delay 14 28 ns
TSU
Input setup time to CLK: bussed
signals
3 7 ns
TSU(ptp)
Input setup time to CLK: point-to-
point signals
5 10, 12 ns
TH Input hold time from CLK 0 0 ns
TRRSU REQ64# to RST# setup time 10* TCYC 10* TCYC ns
TRRH RST# to REQ64# hold time 0 0 ns
Figure 3. PCI Bus Interface Output Timing Measurement
V
TH
V TL
V TEST
PCI_CLK
V
TEST
V STEP (3.3V Signalling)
Output
Delay
Tri-State
Output
output current
≤
leakage current
T
ON
T OFF