Intel 82555 - Manual (Page 18)

82555 — Networking Silicon
14 Datasheet
4.2.2 100BASE-TX Scrambler and MLT-3 Encoder
Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long
transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B
encoder block and presents the scrambled data to the MLT-3 encoder. The 82555 implements the
11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation.
The cipher equation used is:
X[n] = X[n-11] + X[n-9] (mod 2)
The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the
scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to
NRZI coding, but three levels are output instead of two. There are three output levels: positive,
negative and zero. When an NRZ “0” arrives at the input of the encoder, the last output level is
E 11100 1110
F 11101 1111
I 11111
Inter Packet Idle Symbol
(No 4B)
J 11000
1st Start of Packet Symbol
0101
K 10001
2nd Start of Packet Symbol
0101
T 01101 1st End of Packet Symbol
R 00111
2nd End of Packet Symbol
and Flow Control
V 00000 INVALID
V 00001 INVALID
V 00010 INVALID
V 00011 INVALID
H 00100 INVALID
V 00101 INVALID
V 00110 INVALID
V 01000 INVALID
V 01100 INVALID
V 10000 Flow Control S
V 11001 INVALID
Table 2. 4B/5B Encoder
Symbol 5B Symbol Code 4B Nibble Code