Intel 82555 - Manual (Page 21)

Datasheet 17
Networking Silicon — 82555
4.3.1 Adaptive Equalizer
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer
performs adaptation based on the shape of the received signal, equalizing the signal to meet
superior Data Dependent Jitter performance.
4.3.2 Receive Clock and Data Recovery
The clock recovery circuit uses advanced digital signal processing technology to compensate for
various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data
to the MLT-3 decoder.
4.3.3 MLT-3 Decoder, Descrambler, and Receive Digital Section
The 82555 first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B symbols
originated in the transmitter. The descrambling is based on synchronization to the transmit 11-bit
Linear Feedback Shift Register (LFSR) during idle. The data is decoded at the 4B/5B decoder.
Once the 4B symbols are obtained, the 82555 outputs the receive data to the CSMA unit.
4.3.4 100BASE-TX Receive Framing
The 82555 does not differentiate between the fields of the MAC frame containing preamble, start
of frame delimiter, data and CRC. During 100 Mbps reception, the 82555 differentiates between
the idle condition ("L" symbols on the wire) and the preamble or start of frame delimiter. When
two non-consecutive bits are 0b within 10 bits (125 Mbps 5B data coding) the 82555 immediately
asserts the CRS signal. When the “JK” symbols (“11000, 10001”) are fully recognized, the 82555
asserts the RXDV signal and provides the data received on the MII RXD[3:0] to the Receive Clock.
If the “JK” symbol is not recognized (“false carrier sense”), the CRS signal is immediately de-
asserted and RXERR is asserted. Otherwise, the valid data is passed through the MII until the
82555 finds the “TR” (“01101, 00111”) and idle symbols in order to de-assert TXDV and CRS.
4.3.5 100BASE-TX Receive Error Detection and Reporting
In 100BASE-TX mode, the 82555 can detect errors in receive data in a number of ways. Any of the
following conditions is considered an error:
• Link integrity fails in the middle of frame reception.
• The start of stream delimiter “JK” symbol is not fully detected after idle.
• An invalid symbol is detected at the 4B/5B decoder.
• Idle is detected in the middle of a frame (before “TR” is detected).
When any of the above error conditions occurs, the 82555 immediately asserts the Receive Error
signal to the MAC. The RXERR signal is asserted as long as the receive error condition persists on
the receive pair.
4.4 100BASE-TX Collision Detection
100BASE-TX collisions in half duplex mode only are detected similarly to 10BASE-T collision
detection, via simultaneous transmission and reception.