Figure 24. fast link pulse timing parameters, 10 reset timing parameters, Figure 25. reset timing parameters – Intel 82555 User Manual
Page 55: 11 x1 clock specifications, Reset timing parameters, X1 clock specifications
Advertising
Datasheet
51
Networking Silicon — 82555
11.4.10
Reset Timing Parameters
11.4.11
X1 Clock Specifications
T33
T
FLP_BUR_NUM
Number of pulses in one burst
17
33
T34
T
FLP_BUR_WID
FLP Burst width
2
ms
T35
T
FLP_BUR_PER
FLP burst period
8
24
ms
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure 24. Fast Link Pulse Timing Parameters
Fast Link Pulse
T 3 1
T 3 0
T 3 0
Clock Pulse
Data Pulse
Clock Pulse
FLP Bursts
T 3 4
T 3 5
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T36
T
RST_WID
Reset pulse width
500
ns
T37
T
PUP_RST
Power-up to falling edge of reset
500
µ
s
Figure 25. Reset Timing Parameters
Power Up (VCC)
RESET
T37
T36
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T38
T
X1_DC
X1 duty cycle
40
60
%
T39
T
X1_PR
X1 period
±50 PPM
40
ns
Advertising