Intel 82555 - Manual (Page 50)

82555 — Networking Silicon
46 Datasheet
11.4.2 MII Timing Parameters
Figure 14. MII Clocks AC Timing
T1,T2,T3
1.5V
T4,T5,T6 T4,T5,T6
Symbol Parameter Conditions Min Typ Max Units
T7 T
TXDV
TXD[3:0], TXEN, TXERR setup
from the rising edge of TXC
15 25 ns
T8 T
TXH
TXD[3:0], TXEN, TXERR hold
time after the rising edge of TXC
0 ns
T9 T
RXSU
RXD[3:0], RXDV, RXERR valid
before the rising edge of RXC
10 ns
T10 T
RXH
RXD[3:0], RXDV, RXERR hold
time after the rising edge of RXC
10 ns
T11 T
MSU
MDIO setup time to the rising
edge of MDC
MDIO input 10 ns
T12 T
MH
MDIO hold time from the rising
edge of MDC
MDIO input 10 ns
T13 T
MV
MDIO valid from the rising edge
of MDC
MDIO output 300 ns
Figure 15. MII Transmit Timing Parameters
T7
T8
TXCLK
TXD[3:0],
TXER,TXEN
Data Invalid Data Invalid Data Valid