IBM SC34-6814-04 - Manual (Page 524)

in the range X'01' through X'FF' (a leading zero can be omitted). The error
processor name has the form NEPROCxx, where “xx” is the error group index.
A CSECT statement of this name is generated, which causes the error
processor code to be assembled at the end of the node error program module
and to have its own addressability.
If you intend to add your own error processors to the sample node error program,
you should consider the following factors:
v The layout of the communication area. The communication area is described in
detail in Figure 31 on page 489.
v The fact that certain functions cannot be used within DFHZNEP. (See
“Restrictions on the use of EXEC CICS commands” on page 505.)
v The register conventions used by the sample node error program. These are
described in Table 25.
Table 25. Register assignment
Register Use
0 Work register
1 Address of the EXEC parameter list
2 NEB base register (DFHSNEP only)
3 ESB base register (DFHSNEP only) NEP error class register (DFHZNEPI
only)
4 NEP name pointer register (DFHZNEPI only)
5 NEP interface base register (DFHZNEPI only)
6 Work register
7 Work register
8 Work register
9 Work register
10 Code base register
11 Address of the EIB
12 Address of the communication area
13 Address of DFHEISTG storage
14 CSVT base and error processor link register Common subroutine link
register
15 Error processor branch register Common subroutine branch register.
Note:
1. Register 14 must be saved for return from error processors. The
common subroutine vector table (CSVT) is coded after the BALR to the
error processor and so this register is also the CSVT base.
2. Registers 1, 10, 12, 13, 14, and 15 are set up on entry to error
processors.
3. Registers 14 through 11 can be saved by error processors in an area
reserved in EXEC interface storage at label NEPEPRS. Registers 15
through 11 do not need to be restored before return from error
processors.
502 Customization Guide