Sony DVS-9000-C - Manual (Page 27)

1-19
DVS-9000/9000SF
1-8. Checks on Completion of Installation
<Switch>
S301 (A-8) : MIX-CPU reset switch
Pressing this switch initializes the CPU on the MIX-46 board.
S2031 (A-9) : Monitor reset switch
The reset switch that is used to reset the monitor during
maintenance through the terminal.
<Slit land>
SL1, SL2 (G-9) and SL3 (B-6) : JTAG chain switching
They are the slit lands that are used to switch the JTAG
chains. Connect these slit lands to open or to close them so
that the following statuses can be obtained.
SL1 SL2 SL3 Status
Short Open Open The chain of CPLD only is established.
Open Short Short All of the JTAG devices are connected
in chain.
<Connector>
CN2401 (A-7) : TERMINAL pin
This pin is connected to the control terminal and used
during maintenance.
Conforms to RS-232C.
CN3301 (A-5) : ISP common connector
Used only for production in the assembly factory. Used for
program writing into the JTAG device with ISP.
<TEST terminal>
E301 (P-12), E302 (J-13), E306 (P-2), E308 (F-1),
E309 (C-6), E310 (B-1), E321 (A-5) : GND terminal
Use this terminal as the earth point for measuring the
respective check terminals.
TP101, TP102, TP201 (A-4) : + + + + +1.8 V check terminal
+1.8 V-1 to 3 measuring terminal.
TP301 (A-3) : + + + + +3.3 V check terminal
+3.3 V measuring terminal.
TP302 (A-3) : + + + + +12 V check terminal
+12 V measuring terminal.
TP2401 (B-8) : SYS_CLK signal check terminal
Use to check the SYSTEM CLOCK signal.
TP2402 (B-7) : CPU_CLK signal check terminal
Use to check the CPU CLOCK signal.
TP2403 (B-7) : CPU_Q CLK signal check terminal
Use to check the CPU Q CLOCK signal.
TP2404 (B-8) : CPU_H CLK signal check terminal
Use to check the CPU H CLOCK signal.