SOYO SY-K7VTA User Manual

Page 68

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BIOS Setup Utility

SY-K7VTA

64

After you have completed the changes, press [Esc] and follow the

instructions on your screen to save your settings or exit without saving.

The following table describes each field in the Advanced Chipset Features

Menu and how to configure each parameter.

3-4.1 CHIPSET FEATURES SETUP

CHIPSET
FEATURES

Setting

Description

Note

Disabled

DRAM
Timing By
SPD

Enabled

If enable the DRAM will auto
detect the DRAM timing

Default

100MHz

Default

DRAM Clock

133MHz

This item allows you to control the
DRAM speed.

SDRAM Cycle
Length

3
2

When synchronous DRAM is
installed, the number of clock
cycles of CAS latency depends on
the DRAM timing. Do not reset
this field from the default value
specified by the system designer.

Default

Disabled

Default

Bank
Interleave

Enabled

Increase DRAM performance.

Disabled

Default

Memory Hole

Enabled

Some interface cards will map
their ROM address to this area. If
this occurs, select [Enabled] in this
field.

Disabled

PCI master
Pipeline Req

Enabled

Disabled/Enabled PCI Master
Pipeline Req.

Default

Disabled

P2C/C2P
Concurrency

Enabled

This item allows you to
enable/disable the PCI to CPU,
CPU to PCI concurrency.

Default

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