SOYO SY-K7VTA - Manual (Page 71)

BIOS Setup Utility SY-K7VTA
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CHIPSET FEATURES SETUP (Continued)
CHIPSET
FEATURES Setting Description Note
Disabled PCI Delay
Transaction
Enabled
The chipset has an embedded 32-bit
posted write buffer to support delay
transactions cycles. Select Enabled
to support compliance with PCI
specification version 2.1.
Default
Disabled PCI#2 Access
#1 Retry
Enabled
When disabled, PCI#2 will not be
disconnected until access finishes
(difault). When enabled, PCI#2 will
be disconnected if max retries are
attempted without success.
Default
Disabled Default AGP Master 1
WS Write
Enabled When Enabled, writes to the
AGP(Accelerated Graphics Port) are
executed with one wait states.
Disabled Default AGP Master 1
WS Read
Enabled When Enabled, read to the AGP
(Accelerated Graphics Port) are
executed with one wait states.