SOYO SY-K7VTA - Manual (Page 70)

BIOS Setup Utility SY-K7VTA
66
CHIPSET FEATURES SETUP (Continued)
CHIPSET
FEATURES Setting Description Note
Optimal The Clock Control register
(Clk_Ctl) specifies how the
processor will ramp up the
processor clock during low power
modes Default K7 CLK_CTL
Select
Default
Disabled OnChip USB
Enabled
This should be enabled if your
system has a USB installed on the
system board and you want to use it.
Even when so equipped, if you add
a higher performance controller, you
will need to disable this feature.
Default
Disabled Default USB
Keyboard
Support
Enabled Select Enabled if your system
contains a Universal Serial Bus
(USB) controller and you have a
USB keyboard.
Disabled CPU to PCI
Write Buffer
Enabled
When this field is Enabled, writes
from the CPU to the PCI bus are
buffered, to compensate for the
speed differences between the CPU
and the PCI bus. When Disabled,
the writes are not buffered and the
CPU must wait until the write is
complete before starting another
write cycle.
Default
Disabled PCI Dynmic
Bursting
Enabled
When Enabled, every write
transaction goes to the write buffer.
Burstable transactions then burst on
the PCI bus and nonburstable
transactions don’t.
Default
Disabled PCI Master 0
WS Write
Enabled
When Enabled, writes to the PCI
bus are executed with zero wait
states.
Default