SUPER MICRO Computer I2DMR-8G2 - Manual (Page 16)

1-10
Introduction
SUPER i2DMR-8G2/i2DMR-iG2 User's Manual
1-2 Chipset Overview
Built upon the functionality and the capability of the Intel E8870 (870)
chipset, the i2DMR-8G2/i2DMR-iG2 motherboard provides the performance
and feature set required for high-end server platforms with configuration
options optimized for communications, presentation, storage, computation or
database applications. The Intel E8870 chipset consists of the following
four primary components: the Scalable Node Controller (SNC), Server I/O
Hub (SIOH), the Memory Repeater Hub for Synchronous Double Data Rate
Memory(MRH_D) and Scalability Port Switch (SPS) (*Note Below). Comple-
mentary components include the I/O Hub Controller (Intel ICH4), the Firm-
ware Hub (FWH), and the PCI Bus Bridge (P64H2).
The major bus groups are:
Processor system bus: supporting up to two processors and one Scalable
Node Controller (SNC), with a maximum operating frequency of 200
MHz@400 MT/s.
Rambus and SNC Interface: the Interconnection between the SNC and
Memory Repeater Hub (MRH-D), operating at a maximum frequency of 400
MHz.
Synchronous DDR Interface: interface between the MRH-D and up to four
DIMM sockets, operating at the operating clock frequency of 100 MHz per
branch channel.
Scalability Port (SP) Interface: a 400MHz, double-pumped, simultaneous bi-
directional signaling (SBD) interface.
Hub Interface 2.0: interface between the SIOH and the P64H2 using 266
MHz strobes on a 16-bit wide data bus.
Hub Interface 1.5: interface between the SIOH and the ICH4 using 133 MHz
strobes on a 8-bit wide data bus.
Local Firmware Hub (LPC): Interface between the SNC and local firmware.
System Management Bus (SMBus): a subset of the I 2 C serial bus integrated
into the SNC, SPS, and SIOH.
(*Note: The Scalability Port Switch-SPS is not used in the i2DMR-8G2/iG2.)