NXP Semiconductors TFA9812 - Manual (Page 8)

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 8 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I 2 S input
8. Functional description
8.1 General
The TFA9812 is a high-efficiency stereo BTL Class-D amplifier with a digital I 2 S audio
input. It supports all commonly used I 2 S formats.
Figure 1 shows the functional block diagram, which includes the key function blocks of the
TFA9812. In the digital domain the audio signal is processed and converted to a pulse
width modulated signal using BD modulation. A BTL configured power comparator carries
out power amplification.
The audio signal processing path is as follows:
1. The Digital Audio Input (DAI) block translates the I 2 S (-like) input signal into a
standard internal stereo audio stream.
2. The 10-band parametric equalizer can optionally equalize the stereo audio stream.
Both channels have separate equalization streams. It can be used for speaker transfer
curve compensation to optimize the audio performance of applied speakers.
3. Volume control in the TFA9812 is done by attenuation. The attenuation depends on
the volume control settings and the thermal foldback value. Soft mute is also arranged
at this part. In Legacy mode the volume control is done by an on-board
Analog-to-Digital Converter (ADC) which measures the analog voltage on pin 32.
4. The interpolation filter interpolates from 1 fs to the PWM controller sample rate
(2048 fs at 44.1 kHz) by cascading FIR filters.
5. The gain block can boost the signal with 0 dB or +24 dB. Four specific gain settings
are also provided in this block. These specific gain settings are related to maximum
clip levels of < 0.5 %, 10 %, 20 % or 30 % THD at the TFA9812 output. These
maximum clip levels are only valid with the gain boost set to 0 dB and a 0 dBFS input
signal.
6. The power limiter limits the maximum output signal of the TFA9812. The power limiter
settings are 0 dB,
−
1.5 dB,
−
3 dB, and
−
4.5 dB. This function can be used to reduce
the maximum output power delivered to the speakers at a fixed supply voltage and
speaker impedance.
7. The PWM controller block transforms the audio signal into a BD-modulated PWM
signal. The BD-modulation provides a high signal-to-noise performance and
eliminates clock jitter noise.
8. Via four differential comparators the PWM signals are amplified by two BTL power
output stages. By default the left audio signal is connected to channel 1 and the right
audio signal to channel 2.
47 MCLK I/O Master clock input (I 2 S slave mode) or output (I 2 S master
mode)
48 V
SS2
P PCB ground reference
Exposed
die-paddle - P PCB ground reference
Table 3. Pinning description TFA9812 …continued
Pin Symbol Type Description