Tda8752b, Philips semiconductors – NXP Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps TDA8752B User Manual

Page 14

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Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product specification

Rev. 03 — 21 July 2000

14 of 38

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Where:

f

n

= the natural PLL frequency

K

O

= the VCO gain

DR = PLL divider ratio

C

Z

and C

P

= capacitors of the PLL filter.

The other PLL equation is as follows:

(2)

Where:

f

z

= loop filter zero frequency

R = the chosen resistance for the filter

ξ

= the damping factor

F

O

= 0 dB loop gain frequency.

Different resistances for the filter can be programmed via the serial interface. To
improve the performances, the PLL parameters should be chosen so that:

(3)

(4)

The values of R and I

P

must be chosen so that the product is the closest to Lim. In

the event that there are several choices, the couple for which the

ξ

value is the closest

to 1 must be chosen.

A software program called “PLL calculator’” is available on Philips Semiconductor
Internet site to calculate the best PLL parameters.

It is possible to control (independently) the phase of the ADC clock and the phase of
an additional clock output (which could be used to drive a second TDA8752B). For
this, two serial interface-controlled digital phase-shift controllers are included
(controlled by 5-bit registers, phase-shift controller steps are 11.25 deg each on the
whole PLL frequency range).

CKREF is re-synchronized, by the synchro block, on the CKAO clock. The output is
CKREFO (LOW during 8 clock periods). CKAO is the clock at the output of the phase
selector A. This clock can be used as the clocks for CKBO and CKADCO. The timing
is given in

Figure 8

.

Pin COAST is used to disconnect the PLL phase frequency detector during the frame
flyback or the unavailability of the CKREF signal. This signal can normally be derived
from the VSYNC signal.

The clock output is able to drive an external 10 pF load (for the on-chip ADCs).

f

z

1

2

π

R

×

C

Z

×

------------------------------

and

ξ

1
2

---

f

n

f

z

-----

×

=

=

F

O

2

ξ

f

n

R I

P

2

π

DR

×

F

O

×

K

O

-----------------------------------

=

=

F

O

f

ref

----------

0.15

R I

P

0.3

π

DR

×

f

ref

×

K

O

------------------------------------------

Lim

=

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