NXP Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps TDA8752B - Manual (Page 17)

Philips Semiconductors
TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 17 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
9. I 2 C-bus and 3-wire serial bus interfaces
9.1 Register definitions
The configuration of the different registers is shown in Table 4 .
All the registers are defined by a subaddress of 8 bits; bit A4 refers to the mode which
is used with the I
2 C-bus interface; bits Sa3 to Sa0 are the subaddresses of each
register.
Bit Mode, used only with the I 2 C-bus, enables two modes to be programmed:
Mode 0 if bit Mode = 0, each register is programmed independently by giving its
subaddress and its content
Mode 1 if bit Mode = 1, all the registers are programmed one after the other by
giving this initial condition (XXX1 1111) as the subaddress state; thus,
the registers are charged following the predefined sequence of 16 bytes
(from subaddress 0000 to 1101).
9.1.1 Offset register
This register controls the clamp level for the RGB channels. The relationship between
the programming code and the level of the clamp code is given in
Table 5 .
Table 4: I 2 C-bus and 3-wire serial bus registers
Function
name Subaddress Bit definition Default
value
A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB
SUBADDR
− − − − − − − −
X X X Mode Sa3 Sa2 Sa1 Sa0 XXX1 0000
OFFSETR X X X X 0 0 0 0 Or7 Or6 Or5 Or4 Or3 Or2 Or1 Or0 0111 1111
COARSER X X X X 0 0 0 1 Or8 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 0010 0000
FINER X X X X 0 0 1 0 X X X Fr4 Fr3 Fr2 Fr1 Fr0 XXX0 0000
OFFSETG X X X X 0 0 1 1 Og7 Og6 Og5 Og4 Og3 Og2 Og1 Og0 0111 1111
COARSEG X X X X 0 1 0 0 Og8 Cg6 Cg5 Cg4 Cg3 Cg2 Cg1 Cg0 0010 0000
FINEG X X X X 0 1 0 1 X X X Fg4 Fg3 Fg2 Fg1 Fg0 XXX0 0000
OFFSETB X X X X 0 1 1 0 Ob7 Ob6 Ob5 Ob4 Ob3 Ob2 Ob1 Ob0 0111 1111
COARSEB X X X X 0 1 1 1 Ob8 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 0010 0000
FINEB X X X X 1 0 0 0 X X X Fb4 Fb3 Fb2 Fb1 Fb0 XXX0 0000
CONTROL X X X X 1 0 0 1 Vlevel Hlevel Edge Up Do Ip2 Ip1 Ip0 0000 0100
VCO X X X X 1 0 1 0 Z2 Z1 Z0 Vco1 Vco0 Di11 Di10 Di9 0110 0001
DIVIDER
(LSB) X X X X 1 0 1 1 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 1001 0000
PHASEA X X X X 1 1 0 0 X Di0 Cka Pa4 Pa3 Pa2 Pa1 Pa0 X000 0000
PHASEB X X X X 1 1 0 1 X Ckab Ckb Pb4 Pb3 Pb2 Pb1 Pb0 X000 0000