Tda8752b, Philips semiconductors – NXP Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps TDA8752B User Manual

Page 15

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Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product specification

Rev. 03 — 21 July 2000

15 of 38

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

The PLL can be used in three different methods:

The IC can be used as stand-alone with a sampling frequency of up to 110 MHz.

When an RGB signal is at a pixel frequency exceeding 100 to 200 MHz, it is
possible to follow one of the two possibilities given below:

Using one TDA8752B: the sampling rate can be reduced by a factor of two, by

sampling the even pixels in the even frame and the odd pixels in the odd frame.
Pin INV is used to toggle between the frames.

Using two TDA8752Bs: the PLL of the master TDA8752B is used to drive both

ADC clocks. The PLL of the slave TDA8752B is disconnected and the CKBO of
the master TDA8752B is connected to pin CKEXT of the TDA8752B master and
CKAO to the slave TDA8752B. In this case, on pin CKAO CKBO will be the
output (with bit CKAB of the master at logic 1).

The master TDA8752B is used to sample the even pixels and the slave
TDA8752B for odd pixels, using a 180 deg phase shift between the clocks (both
pins CKADCO). The master chip and the slave chip have their pin INV LOW,
which guarantees the 180 deg shift ADC clock drive. It is then necessary to
adjust phase B of the master chip. Special care should be taken with the quality
of the input signal (input settling time).

If CKREFO output signal at the master chip is needed, it is possible to use one
of the two phase A values in order to avoid set-up and hold problems in the
SYNCHRO function; e.g. PHASEA = 100000 and PHASEA = 111111.

When INV is LOW, CKADCO is equal to CKEXT inverted.

t

CKAO

= t

CLK(buffer)

+ t

phase selector

[t

CLK(buffer)

= 10 ns and t

phase selector

=

].

t

CKREFO

= either t

CKAO

if PHASEA

01000 or t

CKAO

+

if PHASEA < 01000.

Fig 8.

Timing diagram.

tCKAO

tCKREFO

FCE470

CKAO

CKREFO

CKREF

t

phase selector

2

π

---------------------------

T

CLK(pixel)

×

T

CLK(pixel)

2

------------------------

T

CLK(pixel)

2

------------------------

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