NXP Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps TDA8752B - Manual (Page 19)

Philips Semiconductors
TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 19 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
The default programmed value is: N
FINE
= 0.
9.1.3 Control register
COAST and HSYNC signals can be inverted by setting the I 2 C-bus control bits
‘Vlevel’ and ‘Hlevel’ respectively. When ‘Vlevel’ and ‘Hlevel’ are set to zero
respectively, COAST and HSYNC are active HIGH.
The bit ‘Edge’ defines the rising or falling edge of CKREF to synchronize the PLL. It
will be on the rising edge if the bit is at logic 0 and on the falling edge if the bit is at
logic 1.
The bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These
bits have to be logic 0 during normal use.
The bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the
bandwidth of the PLL, as shown in
Table 8 .
The default programmed value is as follows:
• Charge pump current = 100
µ
A
• Test bits: no test mode; bits ‘Up’ and ‘Do’ at logic 0
• Rising edge of CKREF: bit ‘Edge’ at logic 0
• COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0.
9.1.4 VCO register
The bits ‘Z2’, ‘Z1’ and ‘Z0’ enable the internal resistance for the VCO filter to be
selected.
Table 7: Gain correspondence (FINE)
N
FINE
Gain V
i
to be full-scale (V)
0 0.825 1.212
31 0.878 1.139
Table 8: Charge pump current control
Ip2 Ip1 Ip0 Current (
µ
A)
0 0 0 6.25
0 0 1 12.5
0 1 0 25
0 1 1 50
1 0 0 100
1 0 1 200
1 1 0 400
1 1 1 700