National Instruments NI PXI-562X - Manual (Page 19)

Chapter 2 Hardware Overview
© National Instruments Corporation 2-5 NI PXI-562x User Manual
Block Diagram
The block diagram below illustrates the operation of the NI 562x.
An explanation of some of these features follows.
Figure 2-3. NI 562x Block Diagram
The digital downconverter is a digital signal processor (DSP) that allows
you to digitally zoom in on data, which reduces the amount of data
transferred into memory and speeds up the rate of data transfer. The digital
downconverter performs frequency-translation, filtering, and decimation
after signals go through the ADC. Refer to the
Incorporating the DDC
section for more information.
The PLL uses a phase detector to synchronize the acquisition clock to either
a 10 MHz reference clock supplied through REF CLK IN or to the CLK 10
signal from the PXI backplane. You can also leave the acquisition clock in
TIO
(Timing and Control)
Digital
Downconverter
Voltage
Controlled
Oscillator
P
X
I
Data Path
Logic
Onboard
Memory
Filter
MITE
(PXI Interface)
ADC
Dither
+
Analog
Input
(INPUT)
Trigger and
Clock Routing
10 MHz
Reference
Input
(REF CLK IN)
EXT TRIG
(PFI)
External Trigger PXI Trigger
CLK 10
Phase
Detector
CalDAC
PLL