National Instruments PC-DIO-96 - Manual (Page 39)

© National Instruments Corporation 4-1 PC-DIO-96 User Manual
Chapter 4
Register-Level Programming
This chapter describes in detail the address and function of each of the PC-DIO-96 control and
status registers. This chapter also includes important information about register-level
programming the PC-DIO-96.
The PC-DIO-96 is a parallel digital I/O board designed around four 82C55A integrated circuits
and one 8253 integrated circuit. The 82C55A is a general-purpose peripheral interface
containing 24 programmable I/O pins. These pins represent the three 8-bit I/O ports (A, B, and
C) of the 82C55A. These ports can be programmed as two groups of 12 signals or as three
individual 8-bit ports. The 8253 is a general-purpose counter/timer that is used to send periodic
interrupts to the host computer. This chapter includes register-level programming information
for the PC-DIO-96, along with program examples written in C and assembly language.
Note: If you plan to use a programming software package such as LabWindows/CVI or
NI-DAQ with your PC-DIO-96 board, you need not read this chapter.
Introduction
The three 8-bit ports of the 82C55A are divided into two groups: group A and group B (two
groups of 12 signals). One 8-bit control word selects the mode of operation for each group. The
group A control bits configure port A (A7 through A0) and the upper 4 bits (nibble) of port C
(C7 through C4). The group B control bits configure port B (B7 through B0) and the lower
nibble of port C (C3 through C0). These configuration bits are defined in the Register
Description for the 82C55A section later in this chapter. Because there are four 82C55A PPI
devices on the board, they are referenced as PPI A, PPI B, PPI C, and PPI D when differentiation
is required.
The three 16-bit counters of the 8253 are accessed through individual data ports and controlled
by one 8-bit control word. The control word selects how the counter data ports are accessed and
what mode the counter uses. The configuration bits are defined in the Register Description for
the 8253 section later in this chapter.
In addition to the 82C55A devices and the 8253 device, there are two registers that select which
onboard signals are capable of generating interrupts. There are two interrupt signals from each
of the four 82C55A devices and two interrupt signals from the 8253 device. Individual enable
bits select which of these 10 signals can generate interrupts. Also, a master enable signal
determines whether the board can actually send a request to the host computer. The
configuration bits for these registers are defined in the Register Description for the Interrupt
Control Registers section later in this chapter.