National Instruments PCI-6110E/6111E User Manual
National Instruments Computer Accessories
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Table of contents
Document Outline
- PCI-6110E/6111E User Manual
- Support
- Important Information
- Contents
- About This Manual
- Chapter 1 Introduction
- Chapter 2 Installation and Configuration
- Chapter 3 Hardware Overview
- Chapter 4 Signal Connections
- Chapter 5 Calibration
- Appendix A Specifications
- Appendix B Cable Connector Descriptions
- Appendix C Common Questions
- Appendix D Customer Communication
- Glossary
- Index
- Figures
- Figure 1-1. The Relationship between the Programming Environment, NI DAQ, and Your Hardware
- Figure 3-1. PCI-6110E Block Diagram
- Figure 3-2. PCI-6111E Block Diagram
- Figure 3-3. Effects of Dither on Signal Acquisition
- Figure 3-4. Analog Trigger Block Diagram for the PCI-6110E
- Figure 3-5. Analog Trigger Block Diagram for the PCI-6111E
- Figure 3-6. Below Low Level Analog Triggering Mode
- Figure 3-7. Above High Level Analog Triggering Mode
- Figure 3-8. Inside Region Analog Triggering Mode
- Figure 3-9. High Hysteresis Analog Triggering Mode
- Figure 3-10. Low Hysteresis Analog Triggering Mode
- Figure 3-11. CONVERT* Signal Routing
- Figure 3-12. RTSI Bus Signal Connection
- Figure 4-1. I/O Connector Pin Assignment for the 611X E Board
- Figure 4-2. 611X E Board PGIA
- Figure 4-3. Differential Input Connections for Ground Referenced Signals
- Figure 4-4. Differential Input Connections for Nonreferenced Signals
- Figure 4-5. Analog Output Connections
- Figure 4-6. Digital I/O Connections
- Figure 4-7. Timing I/O Connections
- Figure 4-8. Typical Posttriggered Acquisition
- Figure 4-9. Typical Pretriggered Acquisition
- Figure 4-10. SCANCLK Signal Timing
- Figure 4-11. EXTSTROBE* Signal Timing
- Figure 4-12. TRIG1 Input Signal Timing
- Figure 4-13. TRIG1 Output Signal Timing
- Figure 4-14. TRIG2 Input Signal Timing
- Figure 4-15. TRIG2 Output Signal Timing
- Figure 4-16. STARTSCAN Input Signal Timing
- Figure 4-17. STARTSCAN Output Signal Timing
- Figure 4-18. CONVERT* Input Signal Timing
- Figure 4-19. CONVERT* Output Signal Timing
- Figure 4-20. SISOURCE Signal Timing
- Figure 4-21. WFTRIG Input Signal Timing
- Figure 4-22. WFTRIG Output Signal Timing
- Figure 4-23. UPDATE* Input Signal Timing
- Figure 4-24. UPDATE* Output Signal Timing
- Figure 4-25. UISOURCE Signal Timing
- Figure 4-26. GPCTR0_SOURCE Signal Timing
- Figure 4-27. GPCTR0_GATE Signal Timing in Edge Detection Mode
- Figure 4-28. GPCTR0_OUT Signal Timing
- Figure 4-29. GPCTR1_SOURCE Signal Timing
- Figure 4-30. GPCTR1_GATE Signal Timing in Edge Detection Mode
- Figure 4-31. GPCTR1_OUT Signal Timing
- Figure 4-32. GPCTR Timing Summary
- Figure B-1. 68 Pin 611X E Series Connector Pin Assignments
- Tables