National Instruments PCI-6110E/6111E - Manual (Page 7)

Table of Contents
PCI-6110E/6111E User Manual viii © National Instruments Corporation
Figures
Figure 1-1. The Relationship between the Programming Environment,
NI-DAQ, and Your Hardware ............................................................... 1-4
Figure 3-1. PCI-6110E Block Diagram ................................................................... 3-1
Figure 3-2. PCI-6111E Block Diagram ................................................................... 3-2
Figure 3-3. Effects of Dither on Signal Acquisition ................................................ 3-5
Figure 3-4. Analog Trigger Block Diagram for the PCI-6110E .............................. 3-6
Figure 3-5. Analog Trigger Block Diagram for the PCI-6111E .............................. 3-7
Figure 3-6. Below-Low-Level Analog Triggering Mode ........................................ 3-7
Figure 3-7. Above-High-Level Analog Triggering Mode ....................................... 3-8
Figure 3-8. Inside-Region Analog Triggering Mode ............................................... 3-8
Figure 3-9. High-Hysteresis Analog Triggering Mode............................................ 3-9
Figure 3-10. Low-Hysteresis Analog Triggering Mode ............................................ 3-9
Figure 3-11. CONVERT* Signal Routing ................................................................. 3-11
Figure 3-12. RTSI Bus Signal Connection ................................................................ 3-13
Figure 4-1. I/O Connector Pin Assignment for the 611X E Board .......................... 4-2
Figure 4-2. 611X E Board PGIA .............................................................................. 4-8
Figure 4-3. Differential Input Connections for Ground-Referenced Signals........... 4-11
Figure 4-4. Differential Input Connections for Nonreferenced Signals................... 4-12
Figure 4-5. Analog Output Connections .................................................................. 4-13
Figure 4-6. Digital I/O Connections......................................................................... 4-14
Figure 4-7. Timing I/O Connections ........................................................................ 4-16
Figure 4-8. Typical Posttriggered Acquisition......................................................... 4-17
Figure 4-9. Typical Pretriggered Acquisition .......................................................... 4-18
Figure 4-10. SCANCLK Signal Timing .................................................................... 4-18
Figure 4-11. EXTSTROBE* Signal Timing .............................................................. 4-19
Figure 4-12. TRIG1 Input Signal Timing .................................................................. 4-20
Figure 4-13. TRIG1 Output Signal Timing................................................................ 4-20
Figure 4-14. TRIG2 Input Signal Timing .................................................................. 4-21
Figure 4-15. TRIG2 Output Signal Timing................................................................ 4-21
Figure 4-16. STARTSCAN Input Signal Timing ...................................................... 4-22
Figure 4-17. STARTSCAN Output Signal Timing.................................................... 4-23
Figure 4-18. CONVERT* Input Signal Timing......................................................... 4-24
Figure 4-19. CONVERT* Output Signal Timing ...................................................... 4-24
Figure 4-20. SISOURCE Signal Timing.................................................................... 4-26
Figure 4-21. WFTRIG Input Signal Timing .............................................................. 4-27
Figure 4-22. WFTRIG Output Signal Timing............................................................ 4-27
Figure 4-23. UPDATE* Input Signal Timing............................................................ 4-28
Figure 4-24. UPDATE* Output Signal Timing ......................................................... 4-28
Figure 4-25. UISOURCE Signal Timing ................................................................... 4-29
Figure 4-26. GPCTR0_SOURCE Signal Timing ...................................................... 4-30
PCI_E.book Page viii Thursday, June 25, 1998 12:55 PM