Figure 4-9. typical pretriggered acquisition, Figure 4-10. scanclk signal timing, Scanclk signal -18 extstrobe* signal -18 – National Instruments PCI-6110E/6111E User Manual
Page 51: Figure 4-9, Typical pretriggered acquisition -18, Figure 4-10. scanclk signal timing -18, Scanclk signal, Extstrobe* signal, Shows the timing for the scanclk signal
Chapter 4
Signal Connections
4-18
© National Instruments Corporation
Figure 4-9. Typical Pretriggered Acquisition
SCANCLK Signal
SCANCLK is an output-only signal that generates a pulse with the
leading edge occurring approximately 50 to 100 ns after an A/D
conversion begins. The polarity of this output is software-selectable but
is typically configured so that a low-to-high leading edge can clock
external analog input multiplexers indicating when the input signal has
been sampled and can be removed. This signal has a 450 ns pulse width
and is software enabled. Figure 4-10
shows the timing for the
SCANCLK signal.
Figure 4-10. SCANCLK Signal Timing
EXTSTROBE* Signal
EXTSTROBE* is an output-only signal that generates either a single
pulse or a sequence of eight pulses in the hardware-strobe mode. An
external device can use this signal to latch signals or to trigger events.
In the single-pulse mode, software controls the level of the
EXTSTROBE* signal. A 10 µs and a 1.2 µs clock are available for
generating a sequence of eight pulses in the hardware-strobe mode.
Don't Care
0
1
2
3
1
0
2
2
2
TRIG1
TRIG2
STARTSCAN
CONVERT*
Scan Counter
t
w
t
w
= 450 ns
t
d
= 50 to 100 ns
t
d
CONVERT*
SCANCLK
PCI_E.book Page 18 Thursday, June 25, 1998 12:55 PM