Pfi1/trig2 (pretrig) signal, Convert* signal – National Instruments PCI-4452 User Manual

Page 47

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Chapter 4

Signal Connections

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National Instruments Corporation

4-17

PCI-4451/4452 User Manual

PFI1/TRIG2 (PRETRIG) Signal

Any PFI pin can externally input the PFI/1TRIG2 (PRETRIG) signal,
which is available as an output on the PFI1/TRIG2 (PRETRIG) pin.

Refer to Figure 4-7 for the relationship of PFI1/TRIG2 to the acquisition
sequence.

As an input, the PFI1/TRIG2 signal is configured in edge-detection mode.
You can select any PFI pin as the source for PFI1/TRIG2 and configure the
polarity selection for either rising or falling edge. The selected edge of the
PFI1/TRIG2 signal initiates the posttriggered phase of a pretriggered
acquisition sequence. In pretriggered mode, the PFI0/TRIG1 signal
initiates the data acquisition. The scan counter indicates the minimum
number of scans before PFI1/TRIG2 is recognized. After the scan counter
decrements to zero, it is loaded with the number of posttrigger scans to
acquire while the acquisition continues. The device ignores the
PFI1/TRIG2 signal if it is asserted prior to the scan counter decrementing
to zero. After the selected edge of PFI1/TRIG2 is received, the device
acquires a fixed number of scans and the acquisition stops. After
PFI1/TRIG2 is received, any additional PFI1/TRIG2 signals are ignored
until the acquisition is restarted. This mode acquires data both before and
after receiving PFI1/TRIG2.

As an output, the PFI1/TRIG2 signal reflects the posttrigger in a
pretriggered acquisition sequence. This is true even if the acquisition is
externally triggered by another PFI signal. The PFI1/TRIG2 signal is not
used in posttriggered data acquisition. The output is an active high pulse
with a pulse width of 50 to 100 ns. This output is set to tri-state at startup.

CONVERT* Signal

The CONVERT* signal is only available as an output on the CONVERT*
pin. The CONVERT* signal reflects the end of delta-sigma conversion on
the ADC. The output is an active-low pulse with a pulse width of 70 to 100
ns. This output is set to tri-state at startup.

User.book Page 17 Tuesday, April 14, 1998 10:20 AM

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