Quatech MPAP-100 User Manual
Page 43
10.7 Receive FIFO timeout
With asynchronous operational modes, the same problem exists. Namely, how is one to
determine when a reception is complete? While the receive pattern detection may be useful here,
the MPAP-100 also offers a timeout feature on the external receive FIFO.
If the external FIFO is not empty and a time interval equal to a specified number of
character-times has elapsed without any further data being received, a receive FIFO interrupt is
generated and RX_FIFO bit in the Interrupt Status Register (see page 43) is set. A character-time
is approximated by counting eight ticks of the bit clock.
To use this feature, the receive clock must be output on TRxCA. It can come from either
an external source or from the channel A baud rate generator. While the RTxCA signal is
typically used for a receive clock, it is not capable of being an output, so the TRxCA signal must
be used instead. Depending on the application, this may force the transmit and receive clocks to
be the same. For most asynchronous applications, this should not pose a problem.