Quatech MPAP-100 User Manual
Page 45
receive unformatted serial data, as it allows the SCC receiver to be manually
placed into sync under program control. This bit is ignored if bit 6 is set (logic 1).
Bit 3:
RCKEN --- Receive Clock Source:
When
set (logic 1), this bit allows the receive clock (RCLK) signal to be generated by
the TRxC pin on channel B of the SCC. When cleared (logic 0), RCLK is
received on pin 17 of the DB-25 connector. In either case, RCLK is always
transmitted on pin 11 of the DB-25 connector.
Bit 2:
TCKEN --- Transmit Clock Source:
When set (logic 1), this bit allows the transmit clock (TCLK) to be generated by
the TRxC pin on channel A of the SCC. When cleared (logic 0), the DTE
receives TCLK on pin 15 of the DB-25 connector. In either case, TCLK is
always transmitted on pin 24 of the DB-25 connector.
Bits 1-0:
Reserved, always 0.
IMPORTANT
Local Loopback and Remote Loopback cannot be enabled
simultaneously. Bits 5 and 4 of the Communications
Register should therefore not be set (logic 1)
simultaneously.