Quatech MPAP-100 - Manual (Page 46)

12 Configuration Register
The Configuration Register is used to set the interrupt source and enable the interface
between the SCC and the external FIFOs. The address of this register is Base+5. Table 10
details the bit definitions of the register.
0 RXSRC FIFOEN 0 INTS0 INTS1 0 1
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Table 10 --- Configuration Register - Read/Write
Bit 7: External Data FIFOs Present --- Reserved, always 1. This
bit can be used as an indicator that external data FIFOs are present. Other
MPA-series products that are not equipped with external data FIFOs, including
MPAP-100 Revision A cards, will return 0 in this bit location.
Bit 6: Reserved, always 0.
Bits 5-4: INTS1, INTS0 --- Interrupt Source and Enable Bits: These
two bits determine the source of the interrupt. The two sources are interrupt from
the SCC (INTSCC), and interrupt on Test Mode (INTTM). Only one interrupt
source can be active at a time. Below is the mapping for these bits. Note that
FIFO-related interrupts will occur only when INTSCC is chosen.
INTTM 1 1
INTSCC 0 1
reserved 0 0
Interrupts disabled 0 0
Interrupt Source INTS0 INTS1
Bit 3: Reserved, always 0.
Bit 2: FIFOEN --- External data FIFO enable: If this
bit is set (logic 1), the external data FIFOs are enabled. If this bit is clear (logic
0), the external data FIFOs are disabled. (See page 31 for full details on FIFO
use.)