Quantum Tape Drive LTO-3 - Manual (Page 48)

Chapter 4 Theory
Data Integrity
34 LTO-3 Tape Drive User’s Guide
Error-correction
Code (ECC)
4
The use of Cyclic Redundancy Checking (CRC), two-level orthogonal
Error Correction Coding (ECC) provides a very low probability of
encountering a hard error. During the read process, ECC correction is
performed on the fly without affecting tape streaming.
There are two levels of Error Correction Coding (ECC). These two levels
are orthogonal — that is, an ECC codeword at one level intersects ECC
codewords at the other level just once, which means there will be only
one common symbol between them. The two levels are called C1 and C2.
C1 ECC 4
As data is written to memory from the Data Processing unit, the DMA /
ECC interface generates C1 ECC bytes and writes them to memory.
As data is written to tape, the C1 ECC is checked and an interrupt
generated if there is an error. The C1 ECC read from memory is the ECC
that is written to tape.
When data is read from tape and stored into memory, C1 ECC is checked.
• If the C1 ECC is good, that codeword pair’s “Valid” bit is set.
• Otherwise, a pointer to the invalid Codeword Pair is passed to the C1
ECC correction engine.
• If the C1 ECC correction engine can correct the error, then the
corrected bytes are written to memory, and the Valid bit is set.
• Otherwise, the Valid bit is left cleared.
As data is read from memory to the Data Processor for decompression,
the C1 ECC is again checked and an interrupt generated if it is not correct.
C2 ECC 4
C2 ECC involves three distinct operations:
1 Encoding
: Generating C2 ECC bytes from data bytes (performed by
ECC co-processor hardware)
2 Decoding
: Generating ECC syndromes from data and ECC bytes,
testing for all-zeroes (performed by ECC co-processor hardware)