Xilinx SP605 - Manual (Page 34)

34 www.xilinx.com SP605 Hardware User Guide
UG526 (v1.8) September 24, 2012
Chapter 1: SP605 Evaluation Board
11. 10/100/1000 Tri-Speed Ethernet PHY
The SP605 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports a GMII interface from the
FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a Halo
HFJ11-1G01E RJ-45 connector with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111 using the settings shown in
Table 1-14 . These settings can be overwritten
via software commands passed over the MDIO interface.
Table 1-15 shows the connections and pin numbers for the PHY.
Table 1-14: PHY Configuration Pins
Pin
Connection on
Board
Bit[2]
Definition and Value
Bit[1]
Definition and Value
Bit[0]
Definition and Value
CFG2 V
CC
2.5V ANEG[3] = 1 ANEG[2] = 1 ANEG[1] = 1
CFG3 V
CC
2.5V ANEG[0] = 1 ENA_XC = 1 DIS_125 = 1
CFG4 V
CC
2.5V HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1
CFG5 V
CC
2.5V DIS_FC = 1 DIS_SLEEP = 1 HWCFG_MD[3] = 1
CFG6 PHY_LED_RX SEL_BDT = 0 INT_POL = 1 75/50 Ω = 0
Table 1-15: Ethernet PHY Connections
U1 FPGA Pin Schematic Net Name
U46 M88E111
Pin Number Pin Name
V20 PHY_MDIO 33 MDIO
R19 PHY_MDC 35 MDC
J20 PHY_INT 32 INT_B
J22 PHY_RESET 36 RESET_B
N15 PHY_CRS 115 CRS
M16 PHY_COL 114 COL
P20 PHY_RXCLK 7 RXCLK
U20 PHY_RXER 8 RXER
T22 PHY_RXCTL_RXDV 4 RXDV
P19 PHY_RXD0 3 RXD0
Y22 PHY_RXD1 128 RXD1
Y21 PHY_RXD2 126 RXD2
W22 PHY_RXD3 125 RXD3
W20 PHY_RXD4 124 RXD4
V22 PHY_RXD5 123 RXD5
V21 PHY_RXD6 121 RXD6