Xilinx ChipScope PLB46 IBA v1.00a User Manual
Page 10
10
DS619 April 7, 2009
Product Specification
Table 2
lists the IBA PLBv46 parameterized features, which control the ports attached to the IBA trigger and stor-
age units. They also are used to configure the storage and match unit options available for each trigger port.
The IBA ports are subdivided into logical groups call match units, as shown in
Table 1
. Each match unit has a set
of parameters that are used to enable and define the trigger port configuration for a specific set of PLBv46 signals.
G62
1=Enable storing MU 10 signals in
the data sample storage buffer.
0=Disable
C_USE_MU_10_ARB_CTL must
be 1 in order to store.
C_MU_10_EN_STORE_ARB_
CTL
0,1
1
Integer
PLB Master Control Bus
G63
Use Master Control Signals
C_USE_MU_11_MSTR_CTL
1,0
0
Integer
G64
Number of match units to use
C_MU_11_NUM_MSTR_CTL
1,2
1
Integer
G65
0=basic, 1=basic w/ edges
C_MU_11_TYPE_MSTR_CTL 0,1
0
Integer
G66
Match unit counter width. 0 means
do not use
C_MU_11_CNT_W_MSTR_
CTL
0,1-32
0
Integer
G67
1=Enable storing MU 11 signals in
the data sample storage buffer.
0=Disable
C_USE_MU_11_MSTR_CTL must
be 1 in order to store.
C_MU_11_EN_STORE_
MSTR_CTL
0,1
0
Integer
PLB Master Size and Type Status
G68
Use Master Size and Type Signals
C_USE_MU_12_MSTR_SZ
1,0
0
Integer
G69
0=basic, 1=basic w/ edges
C_MU_12_TYPE_MSTR_SZ
0,1
0
Integer
G70
Match unit counter width. 0 means
do not use
C_MU_12_CNT_W_MSTR_SZ 0,1-32
0
Integer
G71
1=Enable storing MU 12 signals in
the data sample storage buffer.
0=Disable
C_USE_MU_12_MSTR_SZ must
be 1 in order to store.
C_MU_12_EN_STORE_
MSTR_SZ
0,1
1
Integer
PLB Master Byte Enable
G72
Use M_BE
C_USE_MU_13_MSTR_BE
1,0
0
Integer
G73
0=basic, 1=basic w/ edges
C_MU_13_TYPE_MSTR_BE
0,1
0
Integer
G74
Match unit counter width. 0 means
do not use
C_MU_13_CNT_W_MSTR_B
E
0,1-32
0
Integer
G75
1=Enable storing MU 13 signals in
the data sample storage buffer.
0=Disable
C_USE_MU_13_MSTR_BE must
be 1 in order to store.
C_MU_13_EN_STORE_
MSTR_BE
0,1
1
Integer
Table 2: IBA_PLBv46 Design Parameters (Cont’d)
Generic
Feature/Description
Parameter Name
Allowable
Values
Default
Value
VHDL
Type