Xilinx ChipScope PLB46 IBA v1.00a - Manual (Page 5)

DS619 April 7, 2009 www.xilinx.com 5
Product Specification
The IBA_PLBv46 ports listed in Table 1 connect to the PLBv46 bus. The core divides related ports into 13 match
unit groups (MUs) as shown in the second column of the table. Each match unit group can connect to a trigger port
of the IBA. Certain match unit groups, such as MU_1, are further subdivided to allow more fine control of the sig-
nals attached to a trigger port. For example, PLB_Rst is part of MU_1A and PLB_MRdErr is part of MU_1B but
both will be combined into MU_1 when enabled.
Every match unit label has a match type and match counter width parameter. The match unit type describes the
type of compare operation that can be done with the match unit. The valid values for this type are defined for each
match unit. For instance C_MU_1_TYPE only supports basic and basic with edges because multiple signals make
up this match unit bus; whereas for C_MU_3_TYPE, all compare options are available because this match unit
has only one connected signal bus type. The match counter width allows a user to look for multiple occurrences
of the match event. This counter width is controllable through the C_MU_xx_CNT_W parameter (xx is a place
holder for 1-13). When this parameter is set to 0 only 1 occurrence is counted, otherwise the match event count is
limited by the width of this parameter.
The number of match units to use is defined by the C_MU_xx_NUM parameter. By default if a match unit does
not have the C_MU_xx_NUM parameter then only one match unit is used for the match group. If the
C_MU_xx_NUM parameter is defined, then one or two match units are available for this match group. What this
enables is looking at sequences of this particular match group. For instance in match group 2 you may want a trig-
ger sequence to first look at PLB_PAValid=1 followed by a rising edge on PLB_SaddrAck. For this specific trig-
ger the first match unit is set to look for PLB_PAValid=1 and the second is set for PLB_SaddrAck=R.
The first match unit is labeled 1a and 1b. The 1a group of signals makes up the reset and error flag signals. The
1b group contains master related error signals. The generator allows adding 1a, 1b or both of these groups to the
core via the generic parameters C_USE_MU_1A, and C_USE_MU_1B respectively.
The second match unit has labels 2a, 2b, and 2c. The 2a signals contain 16 of the primitive ports which provide
essential PLB bus transaction information. The 2b signals contain buses that identify widths and master informa-
tion of the active transaction. The 2c label is used for the transaction attribute bus. The three subdivided match
unit groups can be all or individually enabled using the parameters C_USE_MU_2A, C_USE_MU_2B, and
C_USE_MU_2C.
The third, fourth, and fifth match units are used for the address, data write, and data read buses respectively. Each
bus has a dedicated match unit so it can be individually enabled and defined with unique C_MU_xx_TYPE pat-
tern match units.
The 6a and 6b match units are used for the slave side interface. This match unit holds all the control and status
ports of all the slaves on the PLB. Similarly, match units 11, 12 and 13 have all the control and status of all the
masters.
P76 MU_12 M_size[0:
C_PLBV46_NUM_MASTERS*4-1]
Master I Master transfer size
P77 MU_12 PLB_MSSize[0:
C_PLBV46_NUM_MASTERS*2-1] Master I PLB Master slave data bus width indicator
P78 MU_12 M_type[0:
C_PLBV46_NUM_MASTERS*3-1]
Master I Master transfer type
P79 MU_13 M_BE[0:
C_PLBV46_NUM_MASTERS*
C_PLBV46_DWIDTH/8-1]
Master I Master byte enables
Table 1: IBA_PLBv46 Pin Descriptions (Cont’d)
Port MU Signal Name Interface I/O Description