Rainbow Electronics AT45DQ321 - Manual (Page 4)

4 AT45DQ321 [ADVANCE DATASHEET]
DS-45DQ321-031–DFLASH–12/2012
WP (I/O
2
)
Write Protect (I/O
2
): When the WP pin is asserted, all sectors specified for protection by the
Sector Protection Register will be protected against program and erase operations regardless
of whether the Enable Sector Protection command has been issued or not. The WP pin
functions independently of the software controlled protection method. After the WP pin goes
low, the contents of the Sector Protection Register cannot be modified.
The WP pin must be driven at all times or pulled-high using an external pull-up resistor.
If a program or erase command is issued to the device while the WP pin is asserted, the device
will simply ignore the command and perform no operation. The device will return to the idle
state once the CS pin has been deasserted. The Enable Sector Protection command and the
Sector Lockdown command, however, will be recognized by the device when the WP pin is
asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected to
V
CC
whenever possible.
With the Quad-output Read Array command, the WP pin becomes an output pin (I/O
2
) and,
when used with other pins, allows four bits (on I/O
3-0
) of data to be clocked out on every falling
edge of SCK. The QE bit in the Configuration Register must be set in order for the WP pin to
be used as an I/O data pin.
Low
Input/
Output
RESET
(I/O
3
)
Reset (I/O
3
): A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset condition as
long as a low level is present on the RESET pin. Normal operation can resume once the
RESET pin is brought back to a high level.
With the Quad-output Read Array command, the RESET pin becomes an output pin (I/O
3
) and,
when used with other pins, allows four bits (on I/O
3-0
) of data to be clocked out on every falling
edge of SCK. The QE bit in the Configuration Register must be set in order for the RESET pin
to be used as an I/O data pin.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature is not utilized, then it is
recommended that the RESET pin be driven high externally.
Low
Input/
Output
V
CC
Device Power Supply: The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
— Power
GND
Ground: The ground reference for the power supply. GND should be connected to the system
ground.
— Ground
Table 1-1. Pin Configurations (Continued)
Symbol Name and Function
Asserted
State Type