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AT45DQ321 [ADVANCE DATASHEET]
DS-45DQ321-031–DFLASH–12/2012
Figure 25-14.Reset Timing
Note:
1. The CS signal should be in the high state before the RESET signal is deasserted.
CS
SCK
RESET
SO (Output)
High Impedance
High Impedance
SI (Input)
tRST
tREC
tCSS