Teledyne LeCroy Summit Z3-16 PCI Express Multi-lane Exerciser User Manual User Manual
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Summit Z3‐16 PCI Express Multi‐Lane Exerciser User Manual
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Chapter 1
Introduction
The Teledyne LeCroy Summit Z3‐16 Exerciser™ is an advanced Gen1/2/3 PCI Express
verification system capable of generating traffic up to 16 lanes at 8GT/s rates. It blends
sophisticated functionality with practical features to speed the development of
PCI Express™ IP cores, bridges, switches, add‐in boards, and systems.
This user manual describes the installation and operation of the Summit Z3‐16 Exerciser. It
includes a description and examples of the application.
It also describes the installation and operation of the PCI Express Test Platform 16x2.5GT/s
/ 16x5.0GT/s / 16x8.0GT/s which can be purchased optionally.
1.1 Exerciser
Overview
The Summit Z3‐16 is Teledyne LeCroy’s fourth generation exerciser (traffic generator), a
critical test and verification tool to assist engineers in developing and improving the
reliability of their systems. It adds support for PCI Express at the Gen3 data rate of 8 GT/s.
For system testing the Summit Z3 can be used in a device emulation mode, where the
Summit Z3 is directly plugged in to a System Under Test. Hence, the setup is quick and
easy.
For device testing the Summit Z3 is used in combination with the PCI Express Test Platform
16x2.5GT/s / 16x5.0GT/s / 16x8.0GT/s which provides host emulation capabilities for
Summit Z3. The PCI Express Test Platform has two slots, one for the Summit Z3‐16
Exerciser card and the other for the DUT (Device Under Test). Optionally, for Gen1 and
Gen2 host emulation, the Summit Z3 can be used with the passive Teledyne LeCroy PXP‐
100 backplane.
The Summit Z3‐16 builds on the extensive programming and verification test libraries
established for Teledyne LeCroy’s PETrainer™ and Summit Z2‐16 PCI Express Exercisers,
and provides the user a complete suite of test capability, including the ability to test
products to the PCI Express 3.0 specification. When used in combination with the Summit
T3‐16 Protocol Analyzer, engineers have a complete test and development environment
for PCI Express Gen3 related work.