IEI Integration PCIE-Q350 v1.12 - Manual (Page 47)

PCIE-Q350 PICMG 1.3 CPU Card
Page 26
Network Connection.
Can support legacy ASF2.0.
Shared SPI flash with system BIOS
Integrated linear voltage regulator
TCP/UDP checksum and segmentation offload
Receive side scaling
Dual TX and RX queues
802.1p and 802.1q
2.5.5 Intel
®
ICH9DO Low Pin Count (LPC) Interface
The ICH9DO LPC interface complies with the LPC 1.1 specifications. The LPC bus from
the ICH9DO is connected to the following components:
BIOS chipset
Super I/O chipset
Trusted Platform Module (TPM) connector
2.5.6 Intel
®
ICH9DO PCI Interface
The PCI interface on the ICH9DO is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.
PCI Revision 2.3 compliant
33MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to four PCI bus masters
The PCI bus masters are interfaced to the following onboard components:
Two backplane PCI channels
One IT8209 PCI bridge
The bus masters interfaced to the two backplane PCI channels and the two PCI channels
that come from the PCI bridge are all interfaced to the PCI edge connector on the bottom
of the PCIE-Q350 as specified by the PICMG 1.3 form factor.