IEI Integration PCIE-Q350 v1.12 - Manual (Page 53)

PCIE-Q350 PICMG 1.3 CPU Card
Page 32
physical layer (PHY) device with its own Memory Access Controller (MAC) and interfaced
to the Intel® ICH9DO Southbridge through a PCIe x1 lane. The Intel® 82573L GbE
controllers is shown in Figure 2-16 below.
Figure 2-16: Intel® 82573L PCIe GbE Controller
Some of the features of the Intel® 82573L are listed below:
2 Gbps peak bandwidth per direction
PCI Express Rev 1.0a specification
High bandwidth density per pin
Wide,pipelined internal data path architecture
Optimized transmit (Tx) and receive (Rx) queues
32 KB configurable Rx and Tx first-in/first-out (FIFO)
IEEE 802.3x*-compliant flow-control support with software controllable pause
times and threshold values
Programmable host memory Rx buffers (256 B-16 KB)
Descriptor ring management hardware for Tx and Rx
Mechanism for reducing interrupts from Tx/Rx operations
Integrated PHY for 10/100/1000 Mbps (full- and half-duplex)
IEEE 802.3ab* auto-negotiation support
IEEE 802.3ab PHY compliance and compatibility
Tx/Rx IP,TCP,and UDP checksum offloading
Tx TCP segmentation
IEEE 802.1q* Virtual Local Area Network (VLAN) support with VLAN tag