IEI Integration PCIE-Q350 v1.12 - Manual (Page 48)

PCIE-Q350 PICMG 1.3 CPU Card
Page 27
2.5.7 Intel
®
ICH9DO PCIe x1 Bus
The Intel® ICH9DO Southbridge chipset has six PCIe x1 lanes. The four PCIe lanes are
interfaced through a PCIe edge connector at the bottom of the CPU card through a
compatible half-size backplane to either four PCIe x1 expansion cards or one PCIe x4
expansion card on.
One of the remaining PCIe x1 lanes is connected to an Intel® 82566DM GbE controller
and the other PCIe x1 lane is connected to an Intel® 82573L GbE controller.
For more detailed information, please refer to Section 2.6.3.
2.5.8 Intel
®
ICH9DO Real Time Clock
256 bytes of battery backed RAM is provided by the Motorola MC146818B real time clock
(RTC) integrated into the ICH9DO. The RTC operates on a 3V battery and 32.768KHz
crystal. The RTC keeps track of the time and stores system data even when the system is
turned off.
2.5.9 Intel
®
ICH9DO SATA Controller
NOTE:
That SATA drive mode is set in the BIOS. Please refer to the Section
6.3.2 on IDE Configuration on page 113 and Section 6.3.5.2 on AHCI
Configuration on page 127.
The ICH9DO SATA supports three modes of operation:
Native IDE enabled operating system: Two controllers enable all six ports
on the bus. Controller 1 supports Port 0, Port 1, Port 2 and Port 3. Controller 2
supports Ports 4 and Port 5.
Legacy operating system is used: One controller is enabled and only
supports Port 0, Port 1, Port 2 and Port 3.