IEI Integration PCIE-Q350 v1.12 - Manual (Page 78)

PCIE-Q350 PICMG 1.3 CPU Card
Page 57
CN Location: See Figure 4-4
CN Pinouts: See Table 4-5
The digital input/output connector is managed through a Super I/O chip. The DIO
connector pins are user programmable. To see details on how to program the DIO chip,
please refer to Appendix B.
Figure 4-4: DIO Connector Connector Locations