Martel Electronics M2000 - Manual (Page 16)

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7 6 5 4 3 2 1 0
0
RQS
ESB MAV EAV 0 0 0
MSS
RQS Requesting service. The RQS bit is set to 1 whenever bits ESB, MAV, EAV, or ISCB
change from 0 to 1 and are enabled (1) in the SRE. When RQS is 1, the M2000
asserts the SRQ control line on the IEEE-488 interface. You can do a serial poll to
read this bit to see if the M2000 is the source of an SRQ.
MSS Master summary status. Set to 1 whenever bits ESB, MAV, EAV, or ISCB are 1 and
enabled (1) in the SRE. This bit can be read using the *STB? command in serial
remote control in place of doing a serial poll.
ESB Set to 1 when one or more ESR bits are 1.
MAV Message available. The MAV bit is set to 1 whenever data is available in the
M2000’s IEEE-488 interface output buffer.
EAV Error available. An error has occurred and an error is available to be read from the
error queue by using the FAULT? query.
Figure 8. Serial Poll Status Byte (STB) and Service Request Enable (SRE)
Service Request (SRQ) Line
IEEE-488 Service Request (SRQ) is an IEEE-488.1 bus control line that the M2000 asserts to
notify the controller that it requires some type of service. Many instruments can be on the
bus, but they all share a single SRQ line. To determine which instruments set SRQ, the
Controller normally does a serial poll of each instrument. The calibrator asserts SRQ whenev-
er the RQS bit in its Serial Poll Status Byte is 1. This bit informs the controller that the M2000
was the source of the SRQ.
The M2000 clears SRQ and RQS whenever the controller/host performs a serial poll, sends
*CLS, or whenever the MSS bit is cleared. The MSS bit is cleared only when ESB and MAV
are 0, or they are disabled by their associated enable bits in the SRE register being set to 0.
Service Request Enable Register (SRE)
The Service Request Enable Register (SRE) enables or masks the bits of the Serial Poll Status
Byte. The SRE is cleared at power up. Refer to Figure 7 for the bit functions.
Programming the STB and SRE
By resetting (to 0) the bits in the SRE, you can mask (disable) associated bits in the serial poll
status byte. Bits set to 1 enable the associated bit in the serial poll status byte.
Event Status Register (ESR)
The Event Status Register is a two-byte register in which the higher eight bits are always 0,
and the lower eight bits represent various conditions of the M2000. The ESR is cleared (set to
0) when the power is turned on, and every time it is read.
Many of the remote commands require parameters. Improper use of parameters causes com-
mand errors to occur. When a command error occurs, bit CME (5) in the Event Status
Register (ESR) goes to 1 (if enabled in ESE register), and the error is logged in the error
queue.
Event Status Enable (ESE) Register
A mask register called the Event Status Enable register (ESE) allows the controller to enable
or mask (disable) each bit in the ESR. When a bit in the ESE is 1, the corresponding bit in the
ESR is enabled. When any enabled bit in the ESR is 1, the ESB bit in the Serial Poll Status
Byte also goes to 1. The ESR bit stays 1 until the controller reads the ESR or does a device
clear, a selected device clear, or sends the reset or *CLS command to the M2000. The ESE is
cleared (set to 0) when the power is turned on.