ARM Cortex R4F - Manual (Page 10)

List of Tables
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Table 11-6 CP14 debug register map ....................................................................................................... 11-10
Table 11-7 Debug ID Register functions ................................................................................................... 11-11
Table 11-8 Debug ROM Address Register functions ................................................................................ 11-12
Table 11-9 Debug Self Address Offset Register functions ........................................................................ 11-13
Table 11-10 Debug Status and Control Register functions ......................................................................... 11-14
Table 11-11 Data Transfer Register functions ............................................................................................ 11-19
Table 11-12 Watchpoint Fault Address Register functions ......................................................................... 11-19
Table 11-13 Vector Catch Register functions ............................................................................................. 11-20
Table 11-14 Debug State Cache Control Register functions ...................................................................... 11-21
Table 11-15 Debug Run Control Register functions ................................................................................... 11-22
Table 11-16 Breakpoint Value Registers functions ..................................................................................... 11-23
Table 11-17 Breakpoint Control Registers functions ................................................................................... 11-24
Table 11-18 Meaning of BVR bits [22:20] ................................................................................................... 11-25
Table 11-19 Watchpoint Value Registers functions .................................................................................... 11-26
Table 11-20 Watchpoint Control Registers functions .................................................................................. 11-27
Table 11-21 OS Lock Status Register functions ......................................................................................... 11-29
Table 11-22 Authentication Status Register bit functions ........................................................................... 11-29
Table 11-23 PRCR functions ...................................................................................................................... 11-30
Table 11-24 PRSR functions ....................................................................................................................... 11-31
Table 11-25 Management Registers ........................................................................................................... 11-32
Table 11-26 Processor Identifier Registers ................................................................................................. 11-32
Table 11-27 Claim Tag Set Register functions ........................................................................................... 11-33
Table 11-28 Functional bits of the Claim Tag Clear Register ..................................................................... 11-34
Table 11-29 Lock Status Register functions ............................................................................................... 11-35
Table 11-30 Device Type Register functions .............................................................................................. 11-35
Table 11-31 Peripheral Identification Registers .......................................................................................... 11-36
Table 11-32 Fields in the Peripheral Identification Registers ...................................................................... 11-36
Table 11-33 Peripheral ID Register 0 functions .......................................................................................... 11-36
Table 11-34 Peripheral ID Register 1 functions .......................................................................................... 11-37
Table 11-35 Peripheral ID Register 2 functions .......................................................................................... 11-37
Table 11-36 Peripheral ID Register 3 functions .......................................................................................... 11-37
Table 11-37 Peripheral ID Register 4 functions .......................................................................................... 11-37
Table 11-38 Component Identification Registers ........................................................................................ 11-38
Table 11-39 Processor behavior on debug events ..................................................................................... 11-40
Table 11-40 Values in link register after exceptions ................................................................................... 11-42
Table 11-41 Read PC value after debug state entry ................................................................................... 11-44
Table 11-42 Authentication signal restrictions ............................................................................................ 11-52
Table 11-43 Values to write to BCR for a simple breakpoint ...................................................................... 11-58
Table 11-44 Values to write to WCR for a simple watchpoint ..................................................................... 11-59
Table 11-45 Example byte address masks for watchpointed objects ......................................................... 11-60
Table 12-1 VFP system registers ................................................................................................................ 12-4
Table 12-2 Accessing VFP system registers .............................................................................................. 12-4
Table 12-3 FPSID Register bit functions ..................................................................................................... 12-5
Table 12-4 FPSCR Register bit functions ................................................................................................... 12-6
Table 12-5 Floating-Point Exception Register bit functions ........................................................................ 12-8
Table 12-6 MVFR0 Register bit functions ................................................................................................... 12-8
Table 12-7 MVFR1 Register bit functions ................................................................................................... 12-9
Table 12-8 Default NaN values ................................................................................................................. 12-11
Table 12-9 QNaN and SNaN handling ...................................................................................................... 12-12
Table 13-1 Integration Test Registers summary ......................................................................................... 13-4
Table 13-2 Output signals that can be controlled by the Integration Test Registers ................................... 13-5
Table 13-3 Input signals that can be read by the Integration Test Registers .............................................. 13-6
Table 13-4 ITETMIF Register bit assignments ............................................................................................ 13-7
Table 13-5 ITMISCOUT Register bit assignments ...................................................................................... 13-8
Table 13-6 ITMISCIN Register bit assignments .......................................................................................... 13-9
Table 13-7 ITCTRL Register bit assignments ........................................................................................... 13-10
Table 14-1 Definition of cycle timing terms ................................................................................................. 14-4
Table 14-2 Register interlock examples ...................................................................................................... 14-6
Table 14-3 Data Processing Instruction cycle timing behavior if destination is not PC ............................... 14-7
Table 14-4 Data Processing instruction cycle timing behavior if destination is the PC ............................... 14-7