ARM Cortex R4F - Manual (Page 379)

Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-15
ID013010 Non-Confidential, Unrestricted Access
14.9 Branches
This section describes the cycle timing behavior for the
B
,
BL
,
BLX
,
BX
,
BXJ
,
CBNZ
,
CBZ
,
TBB
, and
TBH
instructions. Branches are subject to dynamic and return stack predictions. Table 14-10 shows
example branch instructions and their cycle timing behavior.
Table 14-10 Branch instruction cycle timing behavior
Example instruction Cycles
Memory
cycles
Comments
B<label>, BL<label>a,
BLX<label> a
1 - Correct dynamic prediction
8 - Incorrect dynamic prediction
BX <Rm> b 1 - Correct return stack prediction
9 - Incorrect return stack prediction
BX <cond> <Rm>
b 1 - Correct condition prediction and correct return stack prediction
8 - Incorrect condition prediction
9 - Correct condition prediction and incorrect return stack prediction
BXJ <cond> <Rm> 1 - Condition code fails
9 - Condition code passes
BLX <Rm>
9 - -
BLX <cond> <Rm> 1 - Condition code fails
9 - Condition code passes
CBZ <Rn>, <label> , CBNZ
<Rn>, <label>
1 - Correct condition prediction
8 - Incorrectly predicted
TBB [<Rn>, <Rm>]
c 9 1 Condition code fails
9 1 Condition code passes
TBH [<Rn>, <Rm>, LSL#1]
c 9 1 Condition code fails
9 1 Condition code passes
a. Return stack push.
b. Return stack pop, if condition passes.
c.
<Rn> and <Rm> are Very Early Regs.