2 system control coprocessor registers, 1 register allocation, System control coprocessor registers -9 – ARM Cortex R4F User Manual
Page 93: Table 4-2, Summary of cp15 registers and operations -9

System Control Coprocessor
ARM DDI 0363E
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4.2
System control coprocessor registers
This section describes all of the registers in the system control coprocessor. The section presents
a summary of the registers and descriptions in register order of CRn, Opcode_1, CRm,
Opcode_2.
For more information on using the system control coprocessor and the general method of how
to access CP15 registers, see the ARM Architecture Reference Manual.
4.2.1
Register allocation
Table 4-2 shows a summary of address allocation and reset values for the registers in the system
control coprocessor where:
•
CRn is the register number within CP15
•
Op1 is the Opcode_1 value for the register
•
CRm is the operational register
•
Op2 is the Opcode_2 value for the register.
Table 4-2 Summary of CP15 registers and operations
CRn
Op1
CRm
Op2
Register or operation
Type
Reset value
Page
c0
0
c0
{0, 3, 6-7}
Main ID
Read-only
0x41xFC14x
a
1
Cache Type
Read-only
0x8003C003
2
TCM Type
Read-only
0x00010001
4
MPU Type
Read-only
0x00000000
b
5
Multiprocessor ID
Read-only
0x00000000
c1
0
Processor Feature 0
Read-only
0x00000131
1
Processor Feature 1
Read-only
0x00000001
2
Debug Feature 0
Read-only
0x00010400
3
Auxiliary Feature 0
Read-only
0x00000000
4
Memory Model Feature 0
Read-only
0x00210030
5
Memory Model Feature 1
Read-only
0x00000000
6
Memory Model Feature 2
Read-only
0x01200000
7
Memory Model Feature 3
Read-only
0x00000011
c2
0
Instruction Set Attributes 0
Read-only
0x01101111
c0
0
c2
1
Instruction Set Attributes 1
Read-only
0x13112111
2
Instruction Set Attributes 2
Read-only
0x21232131
3
Instruction Set Attributes 3
Read-only
0x01112131
4
Instruction Set Attributes 4
Read-only
0x00010142
5
Instruction Set Attributes 5
Read-only
0x00000000
6-7
Reserved, Read As Zero
(RAZ)
Read-only
0x00000000
c3-c7
0-7
Reserved, RAZ
Read-only
0x00000000
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