Cirrus Logic AN375 - Manual (Page 15)

AN375
AN375REV4 15
Step 14) Dimmer Compatibility Circuit
Resistor R15, FET Q2, and associated bias circuit components constitute the recommended dimmer
compatibility circuit. The circuit provides a variable current drain to guarantee proper dimmer operation when
the flyback current is not sufficient to keep the dimmer from opening prematurely. The SOURCE pin presents
a variable current sink to GND controlling the sink current through FET Q2. Resistor R15 should be sized to
conduct a 300mA current when the average line voltage is as low as 30V, and it should be as large as possible
to reduce the power dissipated in FET Q2.
Allowing a 1.5V drop across the bridge rectifier, 0.5V for bias of FET Q2, and 3V for the voltage at the
SOURCE pin, resistor R15 is calculated using Equation 22:
3.5 Completing the Design
Step 15) Bias Circuit
The supply voltage V
DD
bias circuit is built using capacitors C2, and C6, diode array D4, resistor R4, and zener
diode Z1 (see Figure 1 on page 5). When AC line voltage is first applied, zener diode Z1 is immediately biased
through capacitor C2 and resistor R4, driving FET Q2 into conduction to provide a start-up voltage to pin VDD.
After start-up, the rectified voltage from the auxiliary winding provides a sufficient voltage across capacitor C1
to bias FET Q1 into conduction sourcing the CS1615/16 supply current.
Step 16) Zero-current Detection
The CS1615/16 uses zero-current detection (ZCD) to minimize switching losses. The ZCD algorithm is
designed to turn ‘ON’ the power FET when the resonant voltage across the FET is at a low point (see Figure 7).
Valley switching reduces the CV
2 losses associated with rerouting charge from the body capacitance of the
FET. Pin FBAUX is designed to monitor the resonant voltage from the auxiliary winding of the flyback/buck-
boost transformer.
The duration of period T1 is determined by the time it takes the primary current to reach peak current I
PK
, and
the duration of period T2 is dependent on the time it takes the secondary current to reach zero. Once the
flyback/buck-boost transformer is built, resistor R
CTRL2
can be adjusted to fine tune the output current.
Adjusting resistor R
CTRL1
changes the switching frequency slightly.
R15
30V 1.5V 0.5V 3V + +   –  
300mA
------------------------------------------------------------------------ 83.3  = =
[Eq. 22]
First Valley
Flyback FET
Voltage
V
Zener
V
INPK
V
Reflected
Figure 7. Switching Waveform of Flyback FET Drain