Cirrus Logic AN375 - Manual (Page 22)

AN375
22 AN375REV4
Calculate minimum and maximum period T1 using Equations 50 and 51:
Calculate minimum and maximum switching frequencies using Equations 52 and 53:
When designing a flyback transformer with an adequate margin, the primary winding should be able to carry
a current slightly greater than peak current I
PK
without saturating. The transformer’s primary winding is
designed for a saturation current I
sat
equal to 550mA, which makes it adequate for a peak current I
PK
equal
to 513.6mA. The transformer turns ratio N is 5.75.
Step 12) Calculate Primary and Secondary Currents
To calculate the flyback transformer primary and secondary RMS currents, the plots in Figure 6 on page 14
are used to establish the ratios P and S. Equation 39 on page 20 defined ratio Z
nom
to be 0.725. Figure 6 on
page 14 is used to determine that ratios P is equal to 27.8% and S is equal to 21.3%. Use Equations 20 and
21 on page 14 to calculate RMS currents I
P(RMS)
and I
S(RMS)
. See Equations 54 and 55:
Step 13) Select an Output Capacitor
The CRD1615-8W is a 120VAC, 60Hz LED driver with an output voltage of 27.9V and an output RMS current
of 250mA. The output capacitor was selected as a standard value of 680
F. See application note AN376
Single Stage Output Ripple Current and the Effect on Load Current in an LED Driver for more details regarding
the calculation and selection of the output capacitor.
Step 14) Dimmer Compatibility Circuit
The CS1515/16 controllers are designed for a specific application. The functional blocks Dimmer
Compatibility, Gate Bias, and Steady State Supply do not change with the output power stage design. This
section of the circuit has been empirically designed and tested against a multitude of dimmer types and proved
compatible. As a general rule, duplicate the circuits and component values given in the customer reference
designs.
4.1 Completing the Design
Step 15) Bias Circuit
The bias circuit design is not related to any specific power converter design and should be replicated as shown
in the CRD1615-8W schematic, which is provided in Figure 8 on page 24.
T1
FREQ min  
L
P
I
PKFREQ max  

V
INPK min  
-------------------------------------------------
2.54mH 465mA 
0.9 2  120 
----------------------------------------------- 7.7 s = = = [Eq. 50]
T1
FREQ max  
L
P
I
PKFREQ min  

V
Start
------------------------------------------------
2.54mH 285mA 
30V
----------------------------------------------- 24 s = = = [Eq. 51]
F
SWFREQ min  

FREQ min  
T1
FREQ max  
-----------------------------------
0.75
24 s
------------- = 31.3kHz = =
[Eq. 52]
F
SWFREQ max  

FREQ max  
T1
FREQ min  
----------------------------------
0.46
7.7 s
--------------- = 59.7kHz = = [Eq. 53]
I
P RMS  
P I
PK
 0.278 513.6mA  142.8mA = = = [Eq. 54]
I
S RMS  
S N I
PK
    0.213 5.75 513.6mA     629mA = = = [Eq. 55]