Cirrus Logic AN375 - Manual (Page 8)

AN375
8 AN375REV4
3.4 Flyback Design
Figure 3 is a composite timing diagram of the primary and secondary winding currents and switching periods.
The flyback design hinges on knowing the peak current I
PK
flowing through power FET Q4.
Constant current I
IN(CC)
is determined by the greater of the TRIAC holding current I
hold
or dimmer current I
fb
required for full-bright power. Most dimmers can deliver nearly 180° of conduction, but some do not start
conducting before 45°.
The flyback is designed to meet the dim mode requirements except for the primary inductance L
P
, which is
calculated to set the desired frequency in PFC mode. The PFC mode frequency profile has a local minimum
at the line peak voltage where the highest EMI energy is generated. The frequency peaks are symmetrically
located at phase angle points 25° and 155° and drop to an absolute minimum near the AC line zero crossing.
The best EMI performance is obtained by setting the switching frequency in PFC mode to be lower than 75kHz
at the line voltage peak.
Step 1) Determine I
IN(CC)
The CS1615/16 switching action is only enabled above 30V for 120V applications and 60V for 230V
applications, losing about 10.4° of conduction at both zero crossings. The entire full-bright power must be
delivered at constant current between phase angles of 45° and 169.6°. The required input power at full bright
is defined by Equation 1:
The average of a sine wave between 45° and 169.6° is 53.8% of the peak value. Therefore the input power is
defined using Equation 2:
Use Equations 1 and 2 to determine full-bright current I
fb
. See Equation 3:
t
i(t)
T1 T2
TT
No Current
T3
Peak Primary Current, I
PK
Primary
Current
Secondary
Current
Figure 3. Timing Diagram of T1, T2, T3, and TT
P
IN
P
OUT

-------------- = [Eq. 1]
P
IN
V
IN avg  
I
fb
 0.538 V
INPK
 I
fb
 = = [Eq. 2]
I
fb
P
OUT
 0.538 V
INPK
 
----------------------------------------------- = [Eq. 3]