Cirrus Logic AN312 - Manual (Page 10)

10 AN312REV2
AN312
Figure 16. 0x14 Mode Typical Connection
(Master and Reference Clock Supplied to Slave Interfaces within Same Chassis when Using CM-1)
Figure 17. Clock Circuit as Used by Mode 0x14 with CM-1 Module
FS1
(LR clock)
SCLK
(Bit clock)
CobraNet Interface
(Slave)
Mode 0x14
FS1
(LR clock)
SCLK
(Bit clock)
MCLK_IN
REFCLK
CobraNet Interface
(Slave)
Mode 0x14
FS1
(LR clock)
SCLK
(Bit clock)
MCLK_IN
MCLK_OUT
24.576 MHz
REFCLK
FS1
CobraNet
Interface
(Master)
Typically Mode
0x00
B eat R eceived
VC X O
24.576 M H z
+/- 100 PP M
D AC
M C LK _IN
M C LK _SE L
R EF C LK _Enable
R E FC LK _ Polarity
R EF C LK
Edge
D etect
M C LK
M U X
Beat
M U X
P hase
D etector
Sam ple
P hase
C ounter
R ST
Loop
Filter
control
C lock
O ut
M C LK _O U T (m aster)
FS1 (w ord)
S C K (bit)
Audio
C lock
G enerator
C lock C onfig
Signal
Path
C ontrol
P ath
H ardw are FP G A Softw are A ctive
Signal
P ath