Cirrus Logic AN312 - Manual (Page 7)

AN312REV2 7
AN312
Figure 11. Clock Circuit as Used by Mode 0x01 with CM-2 and Semiconductors
3.1.4 0x04 Mode - External Master Clock
In External Master Clock Mode, all clocks are derived from an externally supplied master clock of
24.576 MHz. This mode is provided because it is easy to accomplish using the existing clock circuitry. It
is most useful when trying to synchronize one or more CobraNet devices to a distributed Master Clock.
However, it has little practical utility because it is difficult to properly distribute a clock of this frequency
and does not provide a means to ensure synchronization of the audio clocks (SCLK, FS1). Note that
MCLK_OUT is not a copy of MCLK_IN. MCLK_OUT is derived from the VCXO, which is not controlled in
this mode and is not synchronous with the supplied MCLK_IN. When operating in this mode:
• As Conductor: MCLK is sourced directly from MCLK_IN. FS1 and SCLK are derived from MCLK_IN.
• As Performer: MCLK is sourced directly from MCLK_IN. FS1 and SCLK are derived from MCLK_IN.
Figure 12. 0x04 Mode Typical Connection (Synchronization to an Externally-Supplied Master Clock)
B e a t R e c e iv e d
V C X O
2 4 .5 7 6 M H z
+ /- 1 0 0 P P M
D A C
M C L K _ IN
M C L K _ S E L
R E F C L K
M C L K
M U X
B e a t
M U X
P h a s e
D e te c to r
S a m p le
P h a s e
C o u n te r
L o o p
F ilte r
c o n tro l
C lo c k
O u t
M C L K _ O U T (m a s te r )
F S 1 (w o rd )
S C K (b it)
A u d io
C lo c k
G e n e ra to r
C lo c k C o n fig
S ig n a l
P a th
C o n tro l
P a th
E x te rn a l
H a rd w a re
C o b ra N e t
P ro c e s s o r
S o ftw a re
A c tiv e
S ig n a l
P th
CobraNet Interface
FS1
(LR clock)
SCLK
(Bit clock)
MCLK_IN 24.576 MHz