An312 – Cirrus Logic AN312 User Manual
Page 4
4
AN312REV2
AN312
Figure 5. Clock Circuit as Used by Mode 0x00 with CM-2 and Semiconductors
3.1.2
0x10 Mode - Internal Mode with External Sample Synchronization
Note:
This will not work properly with CM-2 modules or semiconductor-based designs due to the ab-
sence of the edge detect circuit in the semiconductor.
This mode is similar to Internal Mode (0x00), but allows synchronization of the derived SCLK and FS1
signals with external clock circuits. It is typically used when it is necessary to synchronize CobraNet clocks
with existing external clock circuitry. When operating in this mode:
•
As Conductor: MCLK, FS1, and SCLK are all generated as in 0x00 Mode. However, the REFCLK in-
put is used to align the clock edges of the generated MCLK, insuring that the audio clocks generated
externally are kept in sync with the CobraNet interface's audio clocks. This mode does not alter the
clock frequency and implies that the REFCLK input should be derived from the MCLK_OUT supplied
by the CobraNet interface (see
•
As Performer: MCLK is generated by the VXCO, which receives frequency adjustments from the beat
packets received over the network interface as in 0x00 Mode. FS1 and SCLK are derived from MCLK.
As above in Conductor Mode, the REFCLK input is used to ensure that the external and CobraNet gen-
erated audio clocks are in sync.
Figure 6. 0x10 Mode Typical Connections (Sync of CobraNet Clocks with External Clock Circuitry)
B e a t R e c e iv e d
V C X O
2 4 .5 7 6 M H z
+ /- 1 0 0 P P M
D A C
M C L K _ IN
M C L K _ S E L
R E F C L K
M C L K
M U X
B e a t
M U X
P h a s e
D e te c to r
S a m p le
P h a s e
C o u n te r
L o o p
F ilte r
c o n tro l
C lo c k
O u t
M C L K _ O U T (m a s te r )
F S 1 (w o rd )
S C K (b it)
A u d io
C lo c k
G e n e ra to r
C lo c k C o n fig
S ig n a l
P a th
C o n tro l
P a th
E x te rn a l
H a rd w a re
C o b ra N e t
P ro c e s s o r
S o ftw a re
A c tiv e
S ig n a l
P a th
Clock Circuit
24.576 MHz
SCLK
REFCLK
MCLK_OUT
Clock In
FS1
FS1
CobraNet Interface