An312 – Cirrus Logic AN312 User Manual
Page 9
AN312REV2
9
AN312
3.1.5
0x14 Mode - External Master Clock with External Sample Clock Synchronization
Note:
This mode operates differently depending on use of the CM-1 or CM-2 CS1810xx/CS4961xx
chip-based products.
3.1.5.1
0x14 Mode for CM-1
In this mode, all clocks are derived from an externally supplied master clock of 24.576 MHz. This mode
is provided primarily to allow synchronization of multiple CobraNet interfaces within the same chassis. It
can also be used, as in 0x10 Mode, to synchronize external clock circuitry derived from an external master
clock. Note that MCLK_OUT is generated by the VCXO in this mode and is not a copy of MCLK_IN. When
operating in this mode:
•
As Conductor: MCLK is supplied by the MCLK_IN input. FS1 and SCLK are derived from MCLK_IN.
As in 0x10 Mode, REFCLK is used to synchronize the clocks.
•
As Performer: MCLK is supplied by the MCLK_IN input. FS1 and SCLK are derived from MCLK_IN.
As in 0x10 Mode, REFCLK is used to synchronize the clocks.
Figure 15. 0x14 Mode Typical Connection
(Synchronization to an Externally-Supplied Master Clock and Word Clock when Using CM-1)
CobraNet Interface
FS1
(LR clock)
SCLK
(Bit clock)
MCLK_IN
24.576 MHz
REFCLK
LR Clock