Cirrus Logic AN312 - Manual (Page 2)

2 AN312REV2
AN312
Figure 1. - CobraNet Clock Circuit for CM-1 Module
Figure 2. CobraNet Clock Circuit for CM-2 Module and Semiconductors
Beat Received
VCXO
24.576MHz
+/- 100 PPM
DAC
MCLK_IN
MCLK_SEL
REFCLK_Enable
REFCLK_Polarity
REFCLK
Edge
Detect
MCLK
MUX
Beat
MUX
Phase
Detector
Sample
Phase
Counter
RST
Loop
Filter
control
Clock
Out
MCLK_OUT (master)
FS1 (word)
SCK (bit)
Audio
Clock
Generator
Clock Config
Signal
Path
Control
Path
Hardware FPGA Software
B e a t R e c e iv e d
V C X O
2 4 .5 76 M H z
+ /- 1 0 0 P P M
D A C
M C LK _ IN
M C L K _ S E L
R E F C L K
M C LK
M U X
B e a t
M U X
P h a s e
D e te c to r
S a m p le
P h a s e
C o u n ter
L o o p
F ilte r
c o n tro l
C lo c k
O u t
M C L K _ O U T (m a s ter )
F S 1 (w o rd )
S C K (b it)
A u d io
C lo c k
G e n e ra to r
C lo ck C o nfig
S ig n a l
P a th
C o n tro l
P a th
E x te rn a l
H a rd w a re
C o b ra N e t
P ro ce s s o r
S o ftw a re