Cirrus Logic CS2100-CP - Manual (Page 16)

CS2100-CP
16 DS840F2
If CLK_IN is removed and then re-applied within t
CS
, the ClkSkipEn bit determines whether PLL_OUT
continues while the PLL re-acquires lock (see Figure 14 ). When ClkSkipEn is disabled and CLK_IN is re-
moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only
for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this
time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will remain continuous
throughout the missing CLK_IN period including the time while the PLL re-acquires lock.
5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN
The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128
Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL directly affects the jitter
transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL
input directly to the PLL output without attenuation. In some applications it is desirable to have a very low
minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others
it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the
PLL without attenuation.
Referenced Control Register Location
ClkSkipEn.............................. “Clock Skip Enable (ClkSkipEn)” on page 28
ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 29
Figure 14. CLK_IN removed for < t
CS
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=1
ClkOutUnl=0 or 1
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0
ClkOutUnl=1
Lock Time
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0
ClkOutUnl=0
Lock Time
t CS
t CS
t CS
= invalid clocks